Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage or trapping layers or other physical phenomena, determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, cellular telephones and removable memory modules.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a bit line. In NAND flash architecture, a column of memory cells are coupled in series with only the first memory cell of the column coupled to a bit line.
One common undesirable phenomenon in NAND technology is referred to as FG-FG coupling, wherein a threshold voltage (Vt) of a memory cell is shifted undesirably as a result of neighboring cells' threshold voltages being shifted during programming. The more negative the initial Vt of a memory cell, the more prone it is to such shifts.
To address FG-FG coupling concerns, memory arrays are often compacted, that is, an attempt is made to tighten the Vt distribution. Such compaction is performed by applying soft programming pulses to all word lines and all un-inhibited bit lines. The voltage applied to the word lines is generally lower than a normal program voltage. The voltage applied to the bit lines is generally near a ground level. Each soft-program pulse is preceded by a verify to determine if any cell within a NAND string has increased to some predetermined value, such as a maximum desired value of an erase Vt in the case of an n-type cell. If so, that string is inhibited from further pulses as further programming pulses may result in programming one or more cells.
This compaction is followed by a verify operation. The verify operation may be performed as an inverted read of the string. The bit lines may be precharged to ground and pulled up through the string. The bit line voltage achieved is a function of the word line voltage and the string's maximum core cell Vt. If the bit line voltage is too high, it means the maximum Vt is too low and the string requires additional soft-program pulses. If the bit line voltage is low enough, the string is inhibited from further pulses. It is important to note that within the string, there are cells whose threshold voltages are more negative than the maximum in that compaction is halted as soon as any cell in the string reaches the predetermined threshold voltage. This can leave many cells having threshold voltages that are far from the desired Vt level.
FIG. 5 is a graph of a hypothetical threshold voltage distribution 502 as might be representative of variations in threshold voltages following erasure of a portion of a memory array. To mitigate the effects of FG-FG coupling, it would be more desirable to have a threshold voltage distribution of the type depicted as dashed line 504. However, a distribution of the type depicted as dashed line 504 is generally not attainable if a individual strings of memory cells each contain a wide distribution of threshold voltages.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative methods of performing compaction and apparatus for performing such methods.